Package org.lwjgl.util.simd
Class SSE
- java.lang.Object
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- org.lwjgl.util.simd.SSE
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public class SSE extends java.lang.Object
Bindings to SSE macros.
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Field Summary
Fields Modifier and Type Field Description static int
_MM_EXCEPT_DENORM
_MM_EXCEPT_DIV_ZERO
_MM_EXCEPT_INEXACT
_MM_EXCEPT_INVALID
_MM_EXCEPT_MASK
_MM_EXCEPT_OVERFLOW
_MM_EXCEPT_UNDERFLOWException state.static int
_MM_FLUSH_ZERO_MASK
_MM_FLUSH_ZERO_OFF
_MM_FLUSH_ZERO_ONFlush zero mask.static int
_MM_MASK_DENORM
_MM_MASK_DIV_ZERO
_MM_MASK_INEXACT
_MM_MASK_INVALID
_MM_MASK_MASK
_MM_MASK_OVERFLOW
_MM_MASK_UNDERFLOWException mask.static int
_MM_ROUND_DOWN
_MM_ROUND_MASK
_MM_ROUND_NEAREST
_MM_ROUND_TOWARD_ZERO
_MM_ROUND_UPRound mode.
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Method Summary
All Methods Static Methods Concrete Methods Modifier and Type Method Description static int
_MM_GET_EXCEPTION_MASK()
Returns the exception mask bits from the MXCSR control and status register.static int
_MM_GET_EXCEPTION_STATE()
Returns the exception state bits from the MXCSR control and status register.static int
_MM_GET_FLUSH_ZERO_MODE()
Returns the flush zero bits from the MXCSR control and status register.static int
_MM_GET_ROUNDING_MODE()
Returns the rounding mode bits from the MXCSR control and status register.static void
_MM_SET_EXCEPTION_MASK(int mask)
Sets the exception mask bits of the MXCSR control and status register.static void
_MM_SET_EXCEPTION_STATE(int mask)
Sets the exception state bits of the MXCSR control and status register.static void
_MM_SET_FLUSH_ZERO_MODE(int mode)
Sets the flush zero bits of the MXCSR control and status register.static void
_MM_SET_ROUNDING_MODE(int mode)
Sets the rounding mode bits of the MXCSR control and status register.
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Field Detail
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_MM_EXCEPT_MASK, _MM_EXCEPT_INVALID, _MM_EXCEPT_DENORM, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT
Exception state.
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_MM_MASK_MASK, _MM_MASK_INVALID, _MM_MASK_DENORM, _MM_MASK_DIV_ZERO, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT
Exception mask.
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_MM_ROUND_MASK, _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO
Round mode.
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_MM_FLUSH_ZERO_MASK, _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF
Flush zero mask.
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Method Detail
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_MM_SET_EXCEPTION_STATE
public static void _MM_SET_EXCEPTION_STATE(int mask)
Sets the exception state bits of the MXCSR control and status register.- Parameters:
mask
- the exception state. One of:EXCEPT_MASK
EXCEPT_INVALID
EXCEPT_DENORM
EXCEPT_DIV_ZERO
EXCEPT_OVERFLOW
EXCEPT_UNDERFLOW
EXCEPT_INEXACT
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_MM_GET_EXCEPTION_STATE
public static int _MM_GET_EXCEPTION_STATE()
Returns the exception state bits from the MXCSR control and status register.
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_MM_SET_EXCEPTION_MASK
public static void _MM_SET_EXCEPTION_MASK(int mask)
Sets the exception mask bits of the MXCSR control and status register.All six exception mask bits are always affected. Bits not set explicitly are cleared.
- Parameters:
mask
- the exception mask. One or more of:MASK_MASK
MASK_INVALID
MASK_DENORM
MASK_DIV_ZERO
MASK_OVERFLOW
MASK_UNDERFLOW
MASK_INEXACT
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_MM_GET_EXCEPTION_MASK
public static int _MM_GET_EXCEPTION_MASK()
Returns the exception mask bits from the MXCSR control and status register.
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_MM_SET_ROUNDING_MODE
public static void _MM_SET_ROUNDING_MODE(int mode)
Sets the rounding mode bits of the MXCSR control and status register.- Parameters:
mode
- the rounding mode. One of:ROUND_MASK
ROUND_NEAREST
ROUND_DOWN
ROUND_UP
ROUND_TOWARD_ZERO
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_MM_GET_ROUNDING_MODE
public static int _MM_GET_ROUNDING_MODE()
Returns the rounding mode bits from the MXCSR control and status register.
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_MM_SET_FLUSH_ZERO_MODE
public static void _MM_SET_FLUSH_ZERO_MODE(int mode)
Sets the flush zero bits of the MXCSR control and status register. FTZ sets denormal results from floating-point calculations to zero.FTZ is a method of bypassing IEEE 754 methods of dealing with invalid floating-point numbers due to underflows. This mode is less precise, but much faster.
- Parameters:
mode
- the flush-to-zero mode. One of:FLUSH_ZERO_MASK
FLUSH_ZERO_ON
FLUSH_ZERO_OFF
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_MM_GET_FLUSH_ZERO_MODE
public static int _MM_GET_FLUSH_ZERO_MODE()
Returns the flush zero bits from the MXCSR control and status register.
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